Master or PhD Computer engineering or EE
APR chip implementation experience with advanced process nodes （28nm and below）
Familiar with P＆R and timing signoff
Familiar with Script languages （shell, python, TCL） or C/C＋＋
Fluent in English speaking
Mathematical is also okay and willing to learn APR and research for new APR flow （Optional）
Proficiency in English is basic requirement. Proficiency in Chinese is a plus.
Seniority > 5 years.
Full chip integration experience is a plus.
APR Lead Manager:
Seniority> 15 years.
Experienced with full chip integration/signoff and tape－out management is needed.