Physical Design Manager & Engineer

求人会社名 : 外資系半導体メーカー

求人ID : 796

  • エージェント取り扱い求人


仕事内容 Physical Design Engineer (ASIC/SoC Place & Route)
Perform the following:
o Chip/Block level floorplan,
o Clock tree synthesis,
o Place & Route,
o RC extraction,
o STA, timing closure,
o IR/EM analysis and fix,
o DRC/LVS/ERC analysis and fix,
o Tape-out sign off.
Customer on-site support.
応募資格 Requirements:
o Bachelor/Master’s degree in Electrical Engineering or Computer Science.
5-15 years Netlist (or RTL)-GDS physical implementation experience.
Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus.
In depth knowledge of major EDA tools/design flows.
Experience with below technology.
Experience in block level implementation, chip integration and signoff.
Experience in Perl/TCL language programming.
Proven record in multi-million gate design production tapeouts.
Experience in any of the following is a plus:
o FinFet Design
o Low-power implementation methodology.
o Advanced timing signoff methodology.
o Independently complete Netlist-GDS P&R, signoff task.
Personal Attributes:
o Aggressive in learning and problem-solving.
o Good communication skill and a good team player.
o Strong project ownership and commitment.
o Self-motivated and can work independently.
勤務地 神奈川県
勤務時間 9:00-17:40
年収・給与 800万円~1200万円


求人会社名 外資系半導体メーカー
概要 大手外資系半導体メーカーになります。
業種 半導体関連

Physical Design Manager & Engineer


HRC株式会社 (本社)



松垣 潔 (マツガキ キヨシ)

コンサルタント歴 : 13年

  • 電気/電子/半導体
  • 土/日でも面談可能
  • 企業と密なリレーション
  • 業界知識豊富
  • 電気・電子・機械・制御