- M.S. degree or above in EE/CS
* Minimum of 3+ years of working experience in digital design, design flow & chip implementation related field.
* Familiar with APR tools (such as Cadence Innovus and Synopsys IC Compiler) & PPA analysis/boost methodology
*Proven capabilities in design flow development, customer’s design flow support & cross functional communication skill would be preferred.
-Proficiency in English is basic requirement. Proficiency in Chinese is a plus.
-Team player with good communication skills, responsibility & flexibility.
-Strong skill to go into technical details to find flow solutions for customers